Publications

Journals: 
  1. J.V.R.Ravindra, M.B.Srinivas, "Delay And Energy E.cient Coding Technique For Capacitive Interconnects" in special issue on Advances in Circuits and Systems for Large Scale Integration in The Journal of Circuits, Systems, and Computers (JCSC). Vol. 16, No. 6 (2007), pp. 929-942.
  2. J.V.R.Ravindra, M.B.Srinivas, "Model Order Reduction of Linear Time Variant High Speed VLSI Interconnects using Frequency Shift Technique" in International Journal of Electronics, Circuits and Systems, World Academy Publishers. Vol. 8, pp.772-776, 2008.
  3. J.V.R.Ravindra, M.B.Srinivas, "Modeling and Simulation of Propagation Delay and Crosstalk of Distributed RLC Interconnects using Diff.erence Model Approach" Communicated to Integration, The VLSI Journal, Elseveir publications
  4. J.V.R.Ravindra, M.B.Srinivas, "Statistical Model for Estimating the E.ect of Process Variations on Delay and Slew Metrics in VLSI Interconnects" Commucicated to IET Journal of Computer and Digital Techniques.
Conferences:

  1. J.V.R.Ravindra, M.B.Srinivas, "Efficient Model Order Reduction Technique using Subspace Iteration Scheme for Linear Time-Varying RLC Circuits" in proceedings of 11th Euromicro Conference on Digital System architectures, Methods and Tools (DSD 2008), September 3-5, 2008, University of Parma, Parma, Italy.
  2. J.V.R.Ravindra, M.B.Srinivas, "Reduced-order Modeling of High Speed VLSI Interconnects using Static Superelement Technique for Nano Meter Designs" in proceedings the IEEE/ACM International Symposium on Nanoscale Architectures (NANO-ARCH), June 12-13, 2008, Anaheim, CA, USA. (Co-located with the 45th Design Automation Conference (DAC 2008))
  3. J.V.R.Ravindra, M.B.Srinivas, "Static Superelement Technique based Model Order Reduction for High Speed Nanometer Designs" in proceedings of the 8th IEEE International Conference on Nanotechnology (IEEE NANO), Aug 18-21, 2008, Texas, USA.
  4. J.V.R.Ravindra, M.B.Srinivas, "Generating Reduced Order Models for High Speed VLSI Interconnects using Balancing-Free Square Root Method" in proceedings of 12th IEEE Workshop on Signal Propagation on Interconnects (SPI 2008). May 12-15, 2008 Avignon, Popes Palace, France. (IEEE Computer Press).
  5. J.V.R.Ravindra, M.B.Srinivas, "Generic Sub-Space Algorithm for Generating Reduced Order Models of Linear Time Varying VLSI Circuits", in proceedings of 18th ACM Great Lakes Symposium on VLSI (GLSVLSI), pp. 111-114, May 4-6, 2008.
  6. J.V.R.Ravindra, M.B.Srinivas, \Modeling of Full-Wave High Speed on Chip RLC Interconnects using Frequency Shift Technique" in proceedings of 9th IEEE Electronics Packaging Technology Conference (EPTC 2007), December 10-12, 2007.
  7. J.V.R.Ravindra, M.B.Srinivas, \Model Order Reduction for RLC Interconnects using Response Dependent Condensation" IEEE Region 10 conference TENCON 2007, October 30- November 2, Taipei, 2007.
  8. K. S. Sainarayanan, C. Raghunandan, J. V. R. Ravindra, M. B. Srinivas, "Bus Coding to Minimize Redundant Bit Transitions" IEEE Region 10 Conference TENCON 2007, October 30- November 2, Taipei, 2007.
  9. J.V.R.Ravindra, Sandeep Saini, Avinash Shukla, M.B.Srinivas, "Sign Extension Based Method Low Power Fast Fourier Transform" in Proceedings of IEEE International Conference on SOC (ISOCC 2007), October 17-19, 2007.
  10. J.V.R.Ravindra, M.B.Srinivas, \Response Dependent Condensation Based macromodeling for Linear Time Varying High Speed VLSI Interconnects" in Proceedings of 7th IEEE International Symposium on Communications and Information Technologies (ISCIT 2007), October 16-19, 2007.
  11. J.V.R.Ravindra, Sandeep Saini, M.B.Srinivas, "A Low- Power, High Speed, Asynchronous VLSI Architecture for FIR Filters", in proceedings 13th IEEE International Symposium Integrated Circuits (ISIC 2007), September 26-28, Singapore, 2007. (Accepted but not Published)
  12. J.V.R.Ravindra, M.B.Srinivas, "Generating Reduced Order Models using Subspace Iteration for Linear RLC Circuits in Nanometer Designs" in ACM SIGARCH /SIGMICRO 2nd International Conference on Nano-Networks (Nano-Net 2007), September 24-26, 2007.
  13. J.V.R.Ravindra, M.B.Srinivas 'Modeling and Analysis of Crosstalk for Distributed RLC Interconnects using Di.erence Model Approach", ACM SIGDA 20th Symposium on Integrated Circuits and System Design (SBCCI 2007), September 3-6, pp. 207-211, September, 2007, Copacabana, Rio de Janeiro, Brazil.
  14. J.V.R.Ravindra, M.B.Srinivas, 'Model Order Reduction Techniques for Nonlinear and Time Varying High Speed RLC Interconnects" session on Work in Progress (WiP) 2007, In connection with 10th EUROMICRO CONFERENCE on DIGITAL SYSTEM DESIGN Architectures, Methods and Tools (DSD 2007), pp. 18-19, August 27 - 31, 2007, Lubeck, Germany.
  15. J.V.R.Ravindra, M.B.Srinivas, "A Statistical Model for Estimating the Effect of Process Variations on Delay and Slew Metrics for VLSI Interconnects", in proceedings of 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007), pp. 325-330, August 27 - 31, 2007, Lubeck, Germany.
  16. K.S.Sainarayanan, J.V.R.Ravindra, C Raghunandan and M B Srinivas, "Coupling Aware Energy-E.cient Data Scrambling On Memory-Processor Interfaces," in 2nd IEEE International Conference on Industrial and Information Systems (ICIIS 2007), August 8-11, 2007, University of Peradeniya, Srilanka.
  17. J.V.R.Ravindra, M.B.Srinivas, "Delay and Skew Analysis of VLSI Interconnects using Difference Model Approach" in Joint Conference on 50th IEEE Mid West Symposium on Circuits and Systems (MWSCAS) and 5th North East Symposium on Circuits and Systems (NEWCAS 2007), August 5-8, 2007, Montreal, Canada.
  18. J.V.R.Ravindra, M.B.Srinivas, "Analytical Crosstalk Model with Inductive Coupling in VLSI Interconnects" in proceedings of 11th IEEE Workshop on Signal Propagation on Interconnects (SPI 2007) May 13-16, 2007 Ruta di Camogli (Genova), Italy.
  19. J.V.R.Ravindra, Navya Chittravu, M. B. Srinivas, "Energy Efficient Spatial Coding Technique for Low Power VLSI Applications" The 2006 International Workshop on System-on-Chip (IWSOC-2006), Dec 27-29, 2006. 
  20. K.S.Sainarayanan, J.V.R.Ravindra, Kiran T. Nath, M.B.Srinivas, "Coding for Minimizing Energy in VLSI Interconnects" in Proceedings of 18th IEEE International Conference on Microelectronics (ICM 2006), pp. 166-169, 16-19 December, Dhahran, Saudi Arabia.
  21. K.S.Sainarayanan, C.Raghunandan, J.V.R.Ravindra, M.B.Srinivas, "Efficient Spatial-Temporal Coding Schemes for Minimizing Delay in Interconnects" in Proceedings of IEEE TENCON 2006, pp. 515-518, 14-17 November, Hong Kong.
  22. K.S.Sainarayanan, C.Raghunandan, J.V.R.Ravindra, M.B.Srinivas, "Modified Area Efficient Temporal Coding Technique for Delay Minimization on VLSI Interconnects" in proceedings of IEEE International Conference on SOC (ISOCC- 06). October 2006, Seoul, Korea.
  23. J.V.R.Ravindra, K. S. Sainarayanan, M. B. Srinivas, "A Novel Low Power Bus Encoding Technique for Minimizing RGB Transitions for LCD Display of Digital Camera" 10th IEEE VLSI Design and Test Symposium 2006 (VDAT-2006) pp. 205-214, August 9 -12, 2006, Goa, India.
  24. K. S. Sainarayanan, J.V.R.Ravindra, M. B. Srinivas "A Low Power Overhead Bus Coding Technique for Minimizing Inductive Crosstalk in VLSI Connectors" SIGDA 15th Inter. Workshop on Logic & Syn. (IWLS), June 7-9, 2006, Vail, Colorado, USA.
  25. K. S. Sainarayanan, J.V.R.Ravindra, M. B. Srinivas, "A Novel Coupling Driven Low Power Bus Coding Technique for Minimizing capacitive Crosstalk in VLSI Interconnects", IEEE International Symposium on Circuits and Systems (ISCAS- 2006), pp 4155-4158, May 21-24, 2006, Island of Kos, Greece.
  26. K.S. Sainarayanan, J.V.R.Ravindra, M. B. Srinivas, "Minimizing Simultaneous Switching Noise (SSN) using Modi.ed Odd/Even Bus-Invert Method" In 3rd IEEE International Workshop on Electronic Design, Test and Applications(DELTA- 2006), January 2006.
  27. J. V.R.Ravindra, K. S. Sainarayanan, M. B. Srinivas, "An Efficient Power Reduction Technique for Low Power Data I/O for Military Applications", In Proc of 24th Digital Avionics Systems Conference, October 2005.
  28. K. S. Sainarayanan, J.V.R.Ravindra, M. B. Srinivas, "A Novel Deep Sub-micron Low Power Bus Coding Technique", In Proc. of International Association of Science and Technology for Development. October 2005.
  29. K.S.Sainarayanan, J.V.R.Ravindra, M.B.Srinivas, "An Efficient Power Reduction Technique for Low Power Data I/O Using Gray Code" in proceedings of IEEE International Conference on Applied Electronics (AE-2005), pp 289-292, September 2005, Pilsen, Czech Republic. 
  30. J.V.R.Ravindra, K. S. Sainarayanan, M. B. Srinivas, "EDGE: Encoding and Decoding of Generic Data for Minimizing Switched Capacitance and Transition Density for Low Power VLSI Applications" In IEEE International Conference on SOC. October 2005.
  31. J.V.R.Ravindra, K. S. Sainarayanan, M. B. Srinivas, "A Novel Bus Coding Technique for Low Power Data Transmission" In IEEE Symposium on VLSI Design and Test Conference (VDAT-2005), pp 263-266, August 2005.

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